NXP Semiconductors

Description

Datasheet Dec 28, 2015 The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). Jan 26, 2015 The 74HC138-Q100; 74HCT138 -Q100 decodes three binary weighted address inputs. (A0, A1 and A2) to eight mutually exclusive outputs (Y0 The 74HCT138 is a high speed CMOS device that is designed to be pin compatable with 74LS low power Schottky types. The device accepts a three bit binary www.fairchildsemi.com. 2. MM. 74HCT138 . Truth Table. H = HIGH Level. L = LOW Level. X = Dont Care. Note 1: G2 = G2A + G2B. Logic Diagram. Inputs. SN74HC595PWR. 74HC595PW. MC74HC595ADTR2G. MM74HC595MTCX. 74HCT138S16-13. SO-16. SN74HCT138DR. 74HCT138D . MC74HCT138ADR2G.